Almost all thermal marketing is a capacity argument. As packages become mixed assemblies of logic, memory and optics, the binding requirement becomes the spread rather than the total.
Read any cooling company’s material and you are reading a capacity argument. Watts removed. Thermal resistance in degrees per watt. Heat transfer coefficient. Kilowatts per rack. Capacity is real and it will keep mattering. But the requirement that decides designs is changing shape, and the vocabulary has not caught up.
The change is in the package. An accelerator package used to be a die. It is now an assembly: logic, stacked high-bandwidth memory, increasingly optical engines, all on one substrate, and those parts do not share a temperature tolerance. High-bandwidth memory has a meaningfully tighter ceiling than logic and sits immediately beside it. Photonic devices are more sensitive again, in a different way. Wavelength and coupling efficiency drift with temperature in ways that logic simply does not, so a photonic engine does not merely run slower when it gets warm, it runs wrong.
Co-packaged optics is the forcing event. Moving optics off the faceplate and onto the package takes a component that used to sit in a pluggable module with its own thermal environment and places it next to a kilowatt-class switch die. Broadcom’s Tomahawk 6 at 102.4 terabits per second, and the Davisson co-packaged variant using TSMC’s optical engines, are the public reference points for where this is heading. Whatever else co-packaged optics does to the network, it creates a thermal requirement that did not previously exist: hold a narrow band across parts with very different tolerances, on the same substrate, at the same moment, under a load that moves.
That is a distribution problem. It is not a bigger version of the capacity problem, and a solution optimized for the total can be the wrong solution for the spread.
Which reframes the competitive question in a way that is genuinely open rather than settled. Every cooling architecture has a claim to uniformity, and the claims are different in kind. Impinging-jet approaches argue spatial addressability: an array can be tuned to the package’s actual power map, targeting the hot regions die by die, because the cooling structure is a designed part rather than a uniform surface. Two-phase approaches argue that boiling holds saturation temperature through the phase change, so the plate stays closer to isothermal, where single-phase water rises roughly ten to fifteen degrees between inlet and outlet and the chips at the outlet end simply run hotter. Microfluidic approaches argue that the channel topology itself can be shaped to the thermal map, and that getting the cooling structure into the silicon removes another conduction layer entirely. These are engineering trades with different costs attached, not a ranking with a winner.
The honest state of the field is that uniformity claims are mostly unmeasured in the way that would settle anything. A capacity number is cheap to publish and easy to compare. A spatial temperature distribution under a realistically non-uniform load, with the memory stack instrumented separately from the logic and the optical engine instrumented separately again, is expensive to produce and rarely shown. Anybody advancing this argument commercially needs their own test data behind it and should present it as a hypothesis until they do. The caveats also differ by architecture and a serious buyer will ask about them: critical heat flux margin and vapour quality control for two-phase, pressure drop through small orifices at the customer’s actual operating point for jets, schedule irreversibility and yield exposure for anything etched into silicon.
There is a second dimension to this that gets even less attention, which is uniformity in time rather than in space. AI workloads do not present a steady load. Power swings hard and fast as work moves through a cluster, and a thermal solution with a large temperature excursion under a transient produces junction temperature variance, and junction temperature variance produces throttling events, and throttling events produce exactly the thing an operator is measuring, which is sustained performance rather than peak performance. A cooling architecture that damps transients well is making a performance argument, not a thermal one, and performance arguments are bought by a different person with a larger budget.
It also pushes the question down a layer, into materials and interfaces. If the requirement is a narrow spread across a mixed package, then the thermal interface between die and cooling structure, the substrate, and the mechanical loading across an uneven assembly all become part of the answer rather than assumed constants. Companies that sell interface materials and mechanical components have historically sold into the sourcing layer as commodities. The uniformity requirement is the first thing in years that gives them a reason to be in an architecture conversation, and most of them have no route into one.
For anyone selling into this, the practical change is to stop leading with the total. Three questions get you further than any capacity claim. What are the per-die temperature ceilings on this package? Which part in the assembly has the tightest tolerance? Has anyone measured the spread across the package under a non-uniform load, or only the maximum? Those questions are hard to answer from marketing material, which means they get routed to an engineer, and an engineer answering them produces a power map. A power map is the second gate of any design-in, and it is not obtainable by asking for it.
The argument against. The counterweight is substantial and should be stated plainly. Capacity is still the binding constraint for the overwhelming majority of deployments today. Single-phase direct-to-chip holds roughly fifty-five percent of the direct-to-chip market in 2026, and credible voices in the industry argue it will remain the default for years on cost, serviceability, supply maturity and roadmap alignment, with real engineering effort going into stretching microchannel designs further up the power curve. Uniformity is the argument for the package layer and for the generation after this one. It is not a reason to tell a customer that the architecture they are shipping is wrong, and a seller who uses it that way will be correctly heard as someone who has read a roadmap and not a requirement.